In the integrated circuit industry today, hundreds of thousands of semiconductor devices are built on a single chip. Every device on the chip must be electrically isolated to ensure that it operates independently without interfering with another. The art of isolating semiconductor devices has become an important aspect of modern metal-oxide-semiconductor (MOS) and bipolar integrated circuit technology for the separation of different devices or different functional regions. With the high integration of the semiconductor devices, improper electrical isolation among devices will cause current leakage, for example junction leakage, consuming a significant amount of power as well as compromising device functionality. Among some examples of reduced functionality include latch-up, which can damage the circuit temporarily, or permanently, noise margin degradation, voltage threshold shift and cross-talk.
Shallow trench isolation (STI), is a preferred electrical isolation technique especially for a semiconductor chip with high integration. STI structures generally involves filling trenches etched into a semiconducting substrate, for example silicon, with a chemical vapor deposition (CVD) silicon oxide (SiO2) which is then planarized by a chemical mechanical polishing (CMP) process which stops on a layer of silicon nitride (e.g., Si3N4) to yield a planar surface.
Shallow trench isolation features with trenches having submicrometer dimensions are effective in preventing latch-up and punch-through phenomena. Broadly speaking, conventional methods of producing a shallow trench isolation feature include: forming a hard mask, for example silicon nitride, over the targeted trench layer, for example including a thermally grown pad oxide layer, patterning a photoresist over the hard mask to define a trench feature, anisotropically etching the hard mask to form a patterned hard mask, and thereafter anisotropically etching the trench feature to form the shallow trench isolation feature. Subsequently, the photoresist is removed (e.g., stripped) and the shallow trench isolation feature is back-filled, with a dielectric material, for example a CVD silicon dioxide, also referred to as STI oxide, followed by thermal treatment and CMP planarization to remove excess STI oxide above the silicon nitride (hardmask) level. Subsequently, the silicon nitride hardmask layer is removed according to a wet etching process using phosphoric acid.
One problem with prior art wet etching processes using phosphoric acid to remove the silicon nitride layer is that the selectivity of silicon nitride to an underlying pad oxide, for example a thermally grown layer of SiO2, is not sufficiently high for manufacturing modern semiconductor devices, for example logic devices using 0.13 micron technologies and smaller, for example 0.1 micron technologies. For example, during the wet etching of the silicon nitride layer, the underlying pad oxide layer is etched to some degree by the phosphoric acid, making the thickness of the pad oxide non-uniform across a process wafer surface. As a result, it has been necessary to remove the remaining pad oxide layer according to a second wet etching process using, for example, hydrofluoric (HF) acid and thermally re-growing another SiO2 layer over the silicon substrate to accommodate subsequent processes.
A problem with etching the pad oxide layer is that frequently, the HF etching solution attacks the STI oxide, for example at the STI trench corners where a thermally grown SiO2 oxide has been grown to line the STI trenches. As a result etching divots at the trench corners where high electrical fields are present during device operation causing device degradation including junction leakage and reverse short channel effects. Another drawback of removing the pad oxide is that a subsequent SiO2 layer, also referred to as a sacrificial oxide must be regrown over the silicon substrate in order to protect the silicon surface and to modify subsequent ion implantation steps forming doped regions in the silicon substrate. For example, during a series of subsequent ion implant processes, ions are implanted at a predetermined distance below the silicon substrate surface and with a predetermined doping profile forming, for example, a retrograde profile. The series of ion implants includes, for example, a voltage threshold adjustment implant and a punch through implant. A uniform layer of SiO2, at the silicon substrate surface is critical for achieving consistent doping profiles and for preventing the phenomenon of ion channeling which adversely affects doping profiles.
There is therefore a need in the semiconductor processing art to develop an improved wet etching composition and method having improved selectivity for etching a metal nitride containing layer overlying a silicon oxide silicon oxide containing layer to avoid or reduce overetching of the silicon oxide layer to improve semiconductor device performance and reliability while improving a device manufacturing process flow.
It is therefore an object of the invention to provide develop an improved wet etching method having improved selectivity for etching a metal nitride containing layer overlying a silicon oxide containing layer to avoid or reduce overetching of the silicon oxide layer to improve semiconductor device performance and reliability while improving a device manufacturing process flow in addition to overcoming other shortcomings in the prior art.